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march 2008 rev 3 1/53 1 STW81103 multi-band rf frequency synthesizer with integrated vcos features integer-n frequency synthesizer dual differential integrated vcos with automatic center frequency calibration: ? 2500 - 3050 mhz (direct output) ? 4350 - 5000 mhz (direct output) ? 1250 - 1525 mhz (internal divider by 2) ? 2175 - 2500 mhz (internal divider by 2) ? 625 - 762.5 mhz (internal divider by 4) ? 1087.5 - 1250 mhz (internal divider by 4) excellent integrated phase noise fast lock time: 150s dual modulus programmable prescaler (16/17 or 19/20) 2 programmable counters to achieve a feedback division ratio from 256 to 65551 (prescaler 16/17) and from 361 to 77836 (prescaler 19/20). programmable reference frequency divider (10 bits) phase frequency comparator and charge pump programmable charge pump current digital lock detector dual digital bus interface: spi and i 2 c bus (fast mode) with 3 bit programmable address (1100a 2 a 1 a 0 ) 3.3 v power supply power down mode (hardware and software) small size exposed pad vfqfpn28 package 5 mm x 5 mm x 1.0 mm process: bicmos 0.35 m sige applications 2.5g and 3g cellular infrastructure equipment catv equipment instrumentation and test equipment other wireless communication systems description the stmicroelectronics STW81103 is an integrated rf synthesizer with voltage controlled oscillators (vcos). showing high performance, high integration, low power, and multi-band performances, STW81103 is a low cost one chip alternative to discrete pll and vcos solutions. STW81103 includes an integer-n frequency synthesizer and two fully integrated vcos featuring low phase noise performance and a noise floor of -155dbc/hz. the combination of wide frequency range vcos (thanks to center- frequency calibration over 32 sub-bands) and multiple output options (direct output, divided by 2 or divided by 4) allows to cover the 625 mhz-762.5 mhz, the 1087.5 mhz-1525 mhz, the 2175 mhz-3050 mhz and the 4350 mhz-5000 mhz bands. the STW81103 is designed with stmicroelectronics advanced 0.35 m sige process. www.st.com
contents STW81103 2/53 contents 1 block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 a and b counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5 phase frequency detector (pfd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.6 lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.7 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.8 voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.8.1 vco selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.8.2 vco frequency calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.8.3 vco voltage amplitude control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.9 output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.9.1 output buffer control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.10 external vco buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6i 2 c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STW81103 contents 3/53 6.1.1 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.2 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.3 byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.4 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.5 single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1.6 multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1.7 current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.3 i 2 c registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.1 write-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.2 read-only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3.3 default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4 vco calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4.1 vco calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 spi digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3 bit tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3.1 default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4 vco calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4.1 vco calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1 direct output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 divided by 2 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.3 divided by 4 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.4 evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
list of tables STW81103 4/53 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. current value vs. selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. vco a performances versus amplitude setting (freq = 2.8 ghz) . . . . . . . . . . . . . . . . . . . 24 table 9. vco b performances vs. amplitude setting (freq = 4.7 ghz) . . . . . . . . . . . . . . . . . . . . . . 25 table 10. ext_pd pin function setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12. multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 13. current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. data and clock timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 15. start and stop timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 16. ack timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 17. write-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 18. functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 19. spi data structure (msb is sent first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 20. address decoder and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 21. spi timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 22. bits at 00h and st1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 23. bits at 01h and st2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 24. order code of the evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 25. package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 26. order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 27. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STW81103 list of figures 5/53 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. vco a (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. vco b (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. vco a (direct output) closed loop phase noise at 2.775 ghz (fstep=200 khz; fpfd=200 khz; icp=2 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. vco b (direct output) closed loop phase noise at 4.675 ghz (fstep=200 khz; fpfd=200 khz; icp=3 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. vco a (div. by 2 output) closed loop phase noise at 1.3876 ghz (fstep=200 khz; fpfd=400 khz; icp=1.5 ma). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. vco b (div. by 2 output) closed loop phase noise at 2.3376 ghz (fstep=200 khz; fpfd=400 khz; icp=2 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. vco a (div. by 4 output) closed loop phase noise at 693.8 mhz (fstep=200 khz; fpfd=800 khz; icp=1 ma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. vco b (div. by 4 output) closed loop phase noise at 1168.8 mhz (fstep=200 khz; fpfd=800 khz; icp=1.5 ma). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. pfd frequency spurs (direct output; fpfd=200 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 12. pfd frequency spurs (div. by 2 output; fpfd=400 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. pfd frequency spurs (div. by 4 output; fpfd=800 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. settling time (final frequency=2.4 ghz; fpfd=400 khz; icp=2.5 ma) . . . . . . . . . . . . . . . 17 figure 15. reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 16. vco divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 17. pfd diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 18. loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 19. vco sub-bands frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 20. data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 21. start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 22. byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 23. data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 24. start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 25. ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 26. spi input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 27. spi timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 28. differential/single-ended output network (match_lc_lump_4g_diff.dsn) . . . . . . . . . 41 figure 29. lc lumped balun and matching network (match_lc_lump_4g.dsn) . . . . . . . . . . . . . . 42 figure 30. evaluation board (evb4g) matching network (match_evb4g.dsn) . . . . . . . . . . . . . . . . 43 figure 31. differential/single-ended output network (match_lc_lump_2g_diff.dsn) . . . . . . . . . 43 figure 32. lc lumped balun for divided by 2 output (match_lc_lump_2g.dsn) . . . . . . . . . . . . . . 44 figure 33. evaluation board (evb2g) matching network (match_evb2g.dsn) . . . . . . . . . . . . . . . . 44 figure 34. lc lumped balun for divided by 4 output (match_lc_lump_1g.dsn) . . . . . . . . . . . . . . 45 figure 35. evaluation board (evb1g) matching network (match_evb1g.dsn) . . . . . . . . . . . . . . . . 46 figure 36. typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 37. ping-pong architecture diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 38. application diagram with external vco (lo output from STW81103) . . . . . . . . . . . . . . . . 49 figure 39. application diagram with external vco (lo output from vco) . . . . . . . . . . . . . . . . . . . . . 49 figure 40. vfqfpn28 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0
block diagram and pin configuration STW81103 6/53 1 block diagram and pin configuration 1.1 block diagram figure 1. block diagram 6#/ "5&& %846#/?).. 6$$?6#/! 633?6#/! 6$$?6#/" 633?6#/" 6$$?%3$ 633?%3$ %846#/?).0 $) 6 " 5& $ 6 ) " 5& %84 6#/ "5& 6$$?"5&6#/ 633?"5&6#/ 6$$?/54"5& /54 " 50 & , 2 4 # 6 4 3 % 4 4 3 % 4 $ 0 ? 4 8 % /54 " 5. & + , # ? & % 2 , , 0 ? $ $ 6 , , 0 ? 3 3 6 4 8 % 2 633?/54"5& 6$$?$)6 633?$)6 6$$?$)6 633?$)6 !$$ ,/!$ !$$ !$$ 6$$?$"53 633?$"53 6#/ $ivider 2%& $ivider "5& 0 & $ # 0 50 $. )#0 ,/#+?$%4 "5& 6$$?#0 633?#0 $"53 3$! $!4! 3#, #,+ $"53?3%, 6#/ #alibrator 6 # / "5 & 6 ) $ 6 ) $
STW81103 block diagram and pin configuration 7/53 1.2 pin configuration figure 2. pin connection (top view) table 1. pin description pin no name description observation 1 vdd_vcoa vco a power supply 2 vdd_div2 divider by 2 power supply 3 vdd_outbuf output buffer power supply 4 outbufp lo buffer positive output open collector 5 outbufn lo buffer negative output open collector 6 vdd_div4 divider by 4 power supply 7 vdd_vcob vco b power supply 8 vdd_esd esd positive rail power supply 9 vctrl vco control voltage qfn 2 8 vdd_vcoa add2 s cl/clk vdd_dbu s s da/data ext_pd add1 add0/load vdd_e s d rext lock_det vdd_cp te s t1 vctrl icp vdd_div2 vdd_outbuf outbufp outbufn vdd_div4 vdd_vcob dbu s _ s el vdd_bufvco extvco_inp extvco_inn vdd_pll ref_clk te s t2
block diagram and pin configuration STW81103 8/53 10 icp pll charge pump output 11 rext external resistance connection for pll charge pump 12 vdd_cp power supply for charge pump 13 test1 test input 1 for test purposes only; must be connected to gnd 14 lock_det lock detector cmos output (i out =4ma) 15 test2 test input 2 for test purposes only; must be connected to gnd 16 ref_clk reference clock input 17 vdd_pll pll digital power supply 18 extvco_inn external vco negative input for test purposes only; must be connected to gnd 19 extvco_inp external vco positive input for test purposes only; must be connected to gnd 20 vdd_bufvco vco buffer power supply 21 dbus_sel digital bus interface select cmos input 22 vdd_dbus spi and i 2 c bus power supply 23 ext_pd power down hardware ?0? device on; ?1? device off cmos input 24 sda/data i2cbus/spi data line cmos bidir schmitt triggered (i out =4ma) 25 scl/clk i2cbus/spi clock line cmos input schmitt triggered 26 add0/load i2cbus address select pin/ spi load line cmos input 27 add1 i2cbus address select pin cmos input; must be connected to gnd in spi mode 28 add2 i2cbus address select pin cmos input; must be connected to gnd in spi mode table 1. pin description (continued) pin no name description observation
STW81103 electrical specifications 9/53 2 electrical specifications 2.1 absolute maximum ratings 2.2 operating conditions table 2. absolute maximum ratings symbol parameter values unit av cc analog supply voltage 0 to 4.6 v dv cc digital supply voltage 0 to 4.6 v t stg storage temperature +150 c esd electrical static discharge - hbm (1) - cdm-jedec standard - mm 4 1.5 0.2 kv 1. the maximum rating of the esd protection circuitry on pin 4 and pin 5 is 800 v. table 3. operating conditions (1) symbol parameter test conditions min. typ. max. units av cc analog supply voltage 3.0 3.3 3.6 v dv cc digital supply voltage 3.0 3.3 3.6 v i vdd1 v dd1 current consumption 90 ma i vdd2 v dd2 current consumption 12 ma t amb operating ambient temperature -40 85 c t j maximum junction temperature 125 c r th j-a junction to ambient package thermal resistance multilayer jedec board 44 c/w r th j-b junction to board package thermal resistance multilayer jedec board 26.3 c/w r th j-c junction to case package thermal resistance multilayer jedec board 6.3 c/w 1. refer to figure 36: typical application diagram .
electrical specifications STW81103 10/53 2.3 digital logic levels 2.4 electrical specifications all electrical specifications are intended for a 3.3 v supply voltage. l table 4. digital logic levels symbol parameter test conditions min. typ. max. units v il low-level input voltage 0.2*vdd v v ih high-level input voltage 0.8*vdd v v hyst schmitt trigger hysteresis 0.8 v v ol low-level output voltage 0.4 v v oh high-level output voltage 0.85*vdd v table 5. electrical specifications symbol parameter condition min. typ. max. unit output frequency range f outa output frequency range with vcoa direct output 2500 3050 mhz divider by 2 1250 1525 mhz divider by 4 625 762.5 mhz f outb output frequency range with vcob direct output 4350 5000 mhz divider by 2 2175 2500 mhz divider by 4 1087.5 1250 mhz vco dividers n vco divider ratio prescaler 16/17 256 65551 prescaler 19/20 361 77836 reference clock and phase frequency detector f ref reference input frequency 10 200 mhz reference input sensitivity (1) 0.35 1 1.5 vpeak r reference divider ratio 2 1023 f pfd pfd input frequency 16 mhz f step frequency step (2) prescaler 16/17 f out / 65551 f out / 256 hz prescaler 19/20 f out / 77836 f out / 361 hz
STW81103 electrical specifications 11/53 charge pump i cp icp sink/source (3) 3-bit programmable 5 ma v ocp output voltage compliance range 0.4 v dd -0.3 v spurious (4) direct output (f pfd =200 khz) -76 dbc divider by 2 (f pfd =400 khz) -82 dbc divider by 4 (f pfd =800 khz) -88 dbc vcos k vcoa vcoa sensitivity (5) lower frequency range 45 65 85 mhz/v intermediate frequency range 60 80 105 mhz/v higher frequency range 85 105 145 mhz/v k vcob vcob sensitivity (5) lower frequency range 45 65 85 mhz/v intermediate frequency range 60 80 100 mhz/v higher frequency range 85 100 130 mhz/v t lk maximum temperature variation for continuous lock (5) (6) vco a 125 c vco b 95 c vcoa pushing (5) 47mhz/v vcob pushing (5) 15 21 mhz/v v ctrl vco control voltage (5) 0.4 3 v lo harmonic spurious (5) -20 dbc i vcoa vcoa current consumption f vco =2.8 ghz; amplitude[11] 30 ma f vco =2.8 ghz; amplitude[00] 16 ma i vcob vcob current consumption f vco =4.7 ghz; amplitude[11] 24 ma f vco =4.7 ghz; amplitude[00] 13 ma i vcobuf vco buffer consumption 15 ma i div2 divider by 2 consumption 17 ma i div4 divider by 4 consumption 14 ma lo output buffer p lo output level 0 dbm r l return loss matched to 50 ohms 15 db i outbuf current consumption div4 buff 26 ma div2 buff 23 ma direct output 39 ma table 5. electrical specifications (continued) symbol parameter condition min. typ. max. unit
electrical specifications STW81103 12/53 external vco frequency range 0.625 5.0 ghz input level -10 +6 dbm current consumption vco internal buffer 28 ma pll miscellaneous i pll current consumption input buffer, prescaler, digital dividers, misc. 12 ma t lock lockup time (5) (7) 25 khz pll bandwidth; within 1 ppm of frequency error 150 s 1. in order to achieve best phase noise performance 1 v peak level is suggested. 2. the frequency step is related to the pfd input frequency as follows: - f step = f pfd for direct output - f step = f pfd /2 for divided by 2 output - f step = f pfd /4 for divided by 4 output 3. see relationship between icp and rext in section 5.7: charge pump . 4. the level of the spurs may change depending on pfd frequenc y, charge pump current, selected channel and pll loop bw. 5. guaranteed by design and specification. 6. when setting a specified output frequency, the vco calibration procedure must be run in order to select the best sub-range for the vco covering the desired frequency. once programmed at the initial temperature t 0 inside the operating temperature range (-40 c to +85 c), the synthesizer is able to maintain the lo ck status only if the temperature drift (in either direction) is within the limit specified by t lk , provided that the final temperature t 1 is still inside the nominal range. if higher t are required the ?vco calibration auto-restart? feature can be enabled, thus allowing to re-start the vco calibration procedure automatically w hen the part loose the lock condition (trigger on lock detector signal). 7. frequency jump from 2250 to 2400 mhz; it includes the ti me required by the vco calibration procedure (7 f pfd cycles with f pfd =400 khz). table 5. electrical specifications (continued) symbol parameter condition min. typ. max. unit
STW81103 electrical specifications 13/53 2.5 phase noise specification table 6. phase noise specification (1) parameter test conditions min. typ. max. unit in-band phase noise floor ? closed loop (2) normalized inband phase noise floor icp=4 ma, pll bw=50 khz; including reference clock contribution -222 dbc/hz inband phase noise floor direct output -222+20log(n)+10log(f pfd )dbc/hz inband phase noise floor divider by 2 -228+20log(n)+10log(f pfd )dbc/hz inband phase noise floor divider by 4 -234+20log(n)+10log(f pfd )dbc/hz pll integrated phase noise ? direct output integrated phase noise 100 hz to 40 mhz f out =4.675 ghz, f pfd =200 khz, f step =200 khz, pll bw = 15 khz, icp=3 ma -34.6 dbc 1.5 rms pll integrated phase noise ? divider by 2 integrated phase noise 100 hz to 40 mhz f out =2.3376 ghz, f pfd =400 khz, f step =200 khz, pll bw=25 khz, icp=2 ma -42.6 dbc 0.6 rms pll integrated phase noise ? divider by 4 integrated phase noise 100 hz to 40 mhz f out =1.1688 ghz, f pfd =800 khz, f step =200 khz, pll bw=35 khz, icp=1.5 ma -49.5 dbc 0.27 rms vco a direct (2500 mhz-3050 mhz) ? open loop (3) phase noise @ 1 khz -59 dbc/hz phase noise @ 10 khz -87 dbc/hz phase noise @ 100 khz -109 dbc/hz phase noise @ 1 mhz -131 dbc/hz phase noise @ 10 mhz -151 dbc/hz phase noise @ 40 mhz -161 dbc/hz vco b direct (4350 mhz-5000 mhz) ? open loop (3) phase noise @ 1 khz -54 dbc/hz phase noise @ 10 khz -82 dbc/hz phase noise @ 100 khz -105 dbc/hz phase noise @ 1 mhz -127 dbc/hz phase noise @ 10 mhz -147 dbc/hz phase noise @ 40 mhz -157 dbc/hz
electrical specifications STW81103 14/53 an evaluation kit is available upon request, including a powerful simulation tool (stwpllsim) that allows a very accurate estimation of the device?s phase noise according to the desired project parameters (vco frequency, selected output stage, reference clock, frequency step, and so on); refer to section 8: application information for more details. vco a with divider by 2 (1250 mhz-1525 mhz) ? open loop (3) phase noise @ 1 khz -65 dbc/hz phase noise @ 10 khz -93 dbc/hz phase noise @ 100 khz -115 dbc/hz phase noise @ 1 mhz -137 dbc/hz phase noise @ 10 mhz -153 dbc/hz phase noise floor @ 40 mhz -155 dbc/hz vco b with divider by 2 (2175 mhz-2500 mhz) ? open loop (3) phase noise @ 1 khz -60 dbc/hz phase noise @ 10 khz -88 dbc/hz phase noise @ 100 khz -111 dbc/hz phase noise @ 1 mhz -132 dbc/hz phase noise @ 10 mhz -150 dbc/hz phase noise floor @ 40 mhz -154 dbc/hz vco a with divider by 4 (625 mhz-762.5 mhz) ? open loop (3) phase noise @ 1 khz -71 dbc/hz phase noise @ 10 khz -99 dbc/hz phase noise @ 100 khz -121 dbc/hz phase noise @ 1 mhz -142 dbc/hz phase noise @ 10 mhz -154 dbc/hz phase noise floor @ 40 mhz -155 dbc/hz vco b with divider by 4 (1087.5 mhz-1250 mhz) ? open loop (3) phase noise @ 1 khz -66 dbc/hz phase noise @ 10 khz -94 dbc/hz phase noise @ 100 khz -117 dbc/hz phase noise @ 1 mhz -138 dbc/hz phase noise @ 10 mhz -153 dbc/hz phase noise floor @ 40 mhz -154 dbc/hz 1. phase noise ssb. vco amplitude setting to value [11]. all cl osed-loop performances are spec ified using a reference clock signal at 76.8 mhz with a phase noise of -135 dbc/hz @1 kh z offset, -145dbc/hz @10khz offset and -149.5 dbc/hz of noise floor. 2. normalized pn = measured pn ? 20log(n) ? 10log(f pfd ), where n is the vco divider ratio (n=b*p+a) and f pfd is the comparison frequency at the pfd input. 3. typical phase noise at centre band frequency. table 6. phase noise specification (1) (continued) parameter test conditions min. typ. max. unit
STW81103 typical performance characteristics 15/53 3 typical performance characteristics phase noise is measured with the agilent e5052a signal source analyzer. all closed-loop measurements are done with f step =200 khz, with the f pfd and charge pump current properly set. the loop filter configuration is depicted in figure 36: typical application diagram , and the reference clock signal is at 76.8 mhz with a phase noise of -135 dbc/hz @1 khz offset, -145 dbc/hz @10 khz offset and -149.5 dbc/hz of noise floor. figure 3. vco a (direct output) open loop phase noise figure 4. vco b (direct output) open loop phase noise figure 5. vco a (direct output) closed loop phase noise at 2.775 ghz (f step =200 khz; f pfd =200 khz; i cp =2 ma) figure 6. vco b (direct output) closed loop phase noise at 4.675 ghz (f step =200 khz; f pfd =200 khz; i cp =3 ma) 1.0 rms 1.5 rms
typical performance characteristics STW81103 16/53 figure 7. vco a (div. by 2 output) closed loop phase noise at 1.3876 ghz (f step =200 khz; f pfd =400 khz; i cp =1.5 ma) figure 8. vco b (div. by 2 output) closed loop phase noise at 2.3376 ghz (f step =200 khz; f pfd =400 khz; i cp =2 ma) 0 . 4 rm s 0 .6 rm s figure 9. vco a (div. by 4 output) closed loop phase noise at 693.8 mhz (f step =200 khz; f pfd =800 khz; i cp =1 ma) figure 10. vco b (div. by 4 output) closed loop phase noise at 1168.8 mhz (f step =200 khz; f pfd =800 khz; i cp =1.5 ma) 0 .19 rm s 0 .2 7 rm s
STW81103 typical performance characteristics 17/53 figure 11. pfd frequency spurs (direct output; f pfd =200 khz) figure 12. pfd frequency spurs (div. by 2 output; f pfd =400 khz) -76 dbc @200khz -84 dbc @400khz figure 13. pfd frequency spurs (div. by 4 output; f pfd =800 khz) figure 14. settling time (final frequency=2.4 ghz; f pfd =400 khz; i cp =2.5 ma) < -90 dbc @800khz
general description STW81103 18/53 4 general description figure 1: block diagram shows the separate blocks that, when integrated, form an integer-n pll frequency synthesizer. the STW81103 consists of two internal low-noise vcos with buffer blocks, a divider by 2, a divider by 4, a low-noise pfd (phase frequency detector), a precise charge pump, a 10-bit programmable reference divider, two programmable counters and a programmable dual- modulus prescaler. the 5-bit a-counter and 12-bit b-counter, in conjunction with the dual- modulus prescaler p/p+1 (16/17 or 19/20), implement an n integer divider, where n = b*p +a. the division ratio of both reference and vco dividers is controlled through the selected digital interface (i 2 c bus or spi). the digital interface type is selected through the proper hardware connection of pin dbus_sel (0 v for i 2 c bus, 3.3 v for spi). all devices operate with a power supply of 3.3 v, and can be powered down when not in use.
STW81103 circuit description 19/53 5 circuit description 5.1 reference input stage the reference input stage is shown in figure 15 . the resistor network feeds a dc bias at the f ref input, while the inverter used as the frequency reference buffer is ac coupled. figure 15. reference frequency input buffer 5.2 reference divider the 10-bit programmable reference counter allows division of the input reference frequency to produce the input clock to the pfd. the division ratio is programmed through the digital interface. 5.3 prescaler the dual-modulus prescaler p/p+1 takes the cml clock from the vco buffer and divides it down to a manageable frequency for the cmos a and b counters. the modulus p is programmable and can be set to 16 or 19. the prescaler is based on a synchronous 4/5 core whose division ratio depends on the state of the modulus input. inv buf vdd f ref power down
circuit description STW81103 20/53 5.4 a and b counters the 5-bit a-counter and 12-bit b-counter, in conjunction with the selected dual modulus (16/17 or 19/20) prescaler, allow the generation of output frequencies that are spaced only by the reference frequency divided by the reference division ratio. the division ratio and the vco output frequency are given by the following formulas: n = b x p + a where f vco : output frequency of vco p: modulus of dual modulus prescaler (16 or 19 selected through the digital interface) b: division ratio of the main counter a: division ratio of the swallow counter f ref : input reference frequency r: division ratio of the reference counter n: division ratio of the pll for the vco divider to work correctly, b absolutely must be greater than a, which can take any value ranging from 0 to 31. the value range of n is either from 256 to 65551 (if p=16) or from 361 to 77836 (p=19). figure 16. vco divider diagram f vco bpa + () r ------------------------------ f ref = 5- b it 12- b it to pfd mod u l us vcobuf+ vcobuf- pre s c a ler 16/17 or 1 9 /20 b-counter a-counter
STW81103 circuit description 21/53 5.5 phase frequency detector (pfd) the pfd takes inputs from the reference and the vco dividers and produces an output proportional to the phase error. the pfd includes a delay gate that controls the width of the anti-backlash pulse. this pulse ensures that there is no dead zone in the pfd transfer function. figure 17 is a simplified schematic of the pfd. figure 17. pfd diagram 5.6 lock detect this signal indicates that the difference between rising edges of both up and down pfd signals is found to be shorter than the fixed delay (roughly 5 ns). the lock detect signal is high when the pll is locked and low when the pll is unlocked. lock detect consumes current only during pll transients. 5.7 charge pump this block drives two matched current sources, i up and i down , which are controlled respectively by up and down pfd outputs. the nominal value of the output current is controlled by an external resistor (connected to the rext input pin) and a 3-bit word that allows selection among 8 different values. the minimum value of the output current is: i min = 2*vbg/rext (vbg~1.17 v) dff r vdd r dff vdd del a y up down abl f ref ref f
circuit description STW81103 22/53 note: the current is output on pin icp. during vco auto-calibration, the icp and vctrl pins are forced to vdd/2. figure 18. loop filter connection table 7. current value vs. selection cpsel2 cpsel1 cpsel0 current value for rext=4.7 k 000i min 0.5 ma 0012*i min 1.0 ma 0103*i min 1.5 ma 0114*i min 2.0 ma 1005*i min 2.5 ma 1016*i min 3.0 ma 1107*i min 3.5 ma 1118*i min 4.0 ma ch a rge p u mp vdd buf vctrl r 3 c2 c1 c a l b it buf c 3 icp r1
STW81103 circuit description 23/53 5.8 voltage controlled oscillators 5.8.1 vco selection the STW81103 integrates two low-noise vcos to cover a wide band from: 2500 mhz to 3050 mhz and from 4350 mhz to 5000 mhz (direct output) 1250 mhz to 1525 mhz and from 2175 mhz to 2500 mhz (selecting divider by 2) 625 mhz to 762.5 mhz and from 1087.5 mhz to 1250 mhz (selecting divider by 4) the frequency range is 2500 mhz-3050 mhz for vco a, and 4350 mhz-5000 mhz for vco b. 5.8.2 vco frequency calibration both vcos can operate on 32 frequency ranges that are selected by adding or subtracting capacitors from the resonator. these frequency ranges are intended to cover the wide band of operation and compensate for process variation on the vco center frequency. the range is automatically selected when the sercal bit is set to 1. the charge pump is inhibited, and the icp and vctrl pins are at vdd/2 volts. the ranges are then tested with this vco input voltage to select the one nearest to the desired output frequency (f out = n*f ref /r). after this selection, the sercal bit is automatically reset to 0 and the charge pump is once again enabled. to enable a fast settle, the pll needs only to perform fine adjustments around vdd/2 on the loop filter to reach f out . figure 19. vco sub-bands frequency characteristics
circuit description STW81103 24/53 the sercal bit should be set to ?1? at each division ratio change. the vco calibration procedure takes approximately 7 periods of the pfd frequency. the maximum allowed f pfd to perform the calibration process is 1 mhz. when using a higher f pfd , follow the steps below: 1. calibrate the vco at the desired frequency with an f pfd less than 1 mhz. 2. set the ratio of the a, b and r dividers for the desired f pfd . vco calibration auto-restart feature the vco calibration auto-restart feature, once activated, allows to restart the calibration procedure when the lock detector reports that the pll has moved to an unlock condition (trigger on ?1? to ?0? transition of lock detector signal). this situation could happen if the device experiences a significant temperature variation. once programmed at the initial temperature t 0 inside the operating temperature range (-40 c to +85 c), the synthesizer is able to maintain the lock status only if the temperature drift (in either direction) is within the limit specified by the t lk parameter, provided that the final temperature t 1 is still inside the nominal range. each vco featured by STW81103 has its specific t lk parameter reported in ta b l e 5 , that is typically lower than the maximum allowable drift ( t max =125; from -40 c to +85 c and vice versa). by enabling the vco calibration auto-restart feature (through the cal_autostart_en bit), the part will be able to select again the proper vco frequency sub-range if the temperature drift exceeds the t lk limit, without any external user command. 5.8.3 vco voltage amplitude control the voltage swing of the vcos can be adjusted over four levels by means of two dedicated programming bits (pll_a1 and pll_a0). higher amplitudes provide best phase noise, whereas lower amplitudes save power. ta b l e 8 gives the voltage swing level expected on the resonator nodes, the current consumption, and the phase noise at 1 mhz. table 8. vco a performances versus amplitude setting (freq = 2.8 ghz) pll_a[1:0] differential voltage swing (vp) current consumption (ma) pn @1 mhz (dbc/hz) 00 1.1 16 -126 01 1.3 19 -127 10 1.9 27 -130 11 2.1 30 -131
STW81103 circuit description 25/53 5.9 output stage the differential output signal of the synthesizer can be selected by software among three different signal paths (direct, divider by 2 and divider by 4) providing multi-band capability. the selection of the output stage is done by programming properly the pd[4:0] bits. the output stage is an open-collector structure which is able to meet different requirements over the desired output frequency range by proper connections on the pcb. refer to section 8: application information for more details on pcb connections. 5.9.1 output buffer control mode this control mode allows to enable/disable the output stage by a hardware control pin (ext_pd, pin#23) while the pll stays locked at the desired frequency; in such a way a very fast switching time is achieved. this feature can be useful in designing a ping-pong architecture saving the cost of an external rf switch. the function of pin#23 (ext_pd) is set with the outbuf_ctrl_en bit as shown in ta b l e 1 0 . table 9. vco b performances vs. amplitude setting (freq = 4.7 ghz) pll_a[1:0] differential voltage swing (vp) current consumption (ma) pn at 1 mhz (dbc/hz) 00 1.1 13 -121 01 1.3 15 -122 10 1.9 22 -126 11 2.1 24 -127 table 10. ext_pd pin function setting outbuf_ctrl_en function of the ext_pd pin ext_pd pin settings 0 device hardware power down ext_pd = 0 v ? device on ext_pd = 3.3 v ? device off 1 output buffer control ext_pd = 0 v ? output stage on ext_pd = 3.3 v ? output stage off
circuit description STW81103 26/53 5.10 external vco buffer although the main benefits of the STW81103 are the two wideband and low-noise vcos, the capability to use an external vco is also provided. the external vco buffer is able to manage a signal coming from an external vco in order to build a synthesizer using the STW81103 only as pll ic. the output signal of the synthesizer can also be taken from the output section of the STW81103 (direct, divided by 2 or divided by 4 by) by properly setting the pd[4:0] bits, thus providing additional flexibility. the external vco signal can range from 625 mhz up to 5 ghz and its minimum power level must be -10 dbm.
STW81103 i 2 c bus interface 27/53 6 i 2 c bus interface the i 2 c bus interface is selected by hardware connection of pin #21 (dbus_sel) to 0 v. data is transmitted from microprocessor to the STW81103 through the 2-wire (sda and scl) i 2 c bus interface. the STW81103 is always a slave device. the i 2 c bus protocol defines any device that sends data on the bus as a transmitter, and any device that reads the data as a receiver. the device controlling the data transfer is the master, and the others are slaves. the master always initiates the transfer and provides the serial clock for synchronization. the STW81103 i 2 c bus supports fast mode operation (clock frequency up to 1mhz). 6.1 general features 6.1.1 data validity data changes on the sda line must only occur when the scl is low. sda transitions while the clock is high are used to identify a start or stop condition. figure 20. data validity 6.1.2 start and stop conditions start condition a start condition is identified by a transition of the data bus sda from high to low while the clock signal scl is stable in the high state. a start condition must precede any data transfer command. stop condition a stop condition is identified by a transition of the data bus sda from low to high while the clock signal scl is stable in the high state. a stop condition terminates communications between the STW81103 and the bus master. s da s cl d a t a line ch a nge s t ab le d a t a d a t a v a lid a llowed
i 2 c bus interface STW81103 28/53 figure 21. start and stop conditions 6.1.3 byte format and acknowledge every byte put on the sda line must be 8 bits long, starting with the most significant bit (msb), and be followed by an acknowledge bit to indicate a successful data transfer. the transmitter releases the sda line after sending 8 bits of data. during the 9th clock pulse, the receiver pulls the sda line low to acknowledge the receipt of 8 bits of data. figure 22. byte format and acknowledge 6.1.4 device addressing the master must first initiate with a start condition to communicate with the STW81103, and then send 8 bits (msb first) on the sda line which correspond to the device select address and the read or write mode. the first seven msbs are the device address identifier, which corresponds to the i 2 c bus definition. for the STW81103, the address is set at ?1100a 2 a 1 a 0 ?, 3 bits programmable. the 8th bit (lsb) is the read or write (rw) operation bit, which is set to 1 in read mode and to 0 in write mode. following a start condition, the STW81103 identifies the device address on the bus and, if matched, acknowledges the identification on the sda bus during the 9th clock pulse. s da s cl s tart s top s d a s c l s tart / / / / acknowledgement from receiver 8 9 1 m s b 2 3 7
STW81103 i 2 c bus interface 29/53 6.1.5 single-byte write mode following a start condition, the master sends a device select code with the rw bit set to 0. the STW81103 sends an acknowledge and waits for the 1-byte internal sub-address that provides access to the internal registers. after receiving the sub-address internal byte, the STW81103 again responds with an acknowledge. a single-byte write to sub-address 00h changes the functional_mode register, a single-byte write with sub-address 04h changes the control register, and so on. 6.1.6 multi-byte write mode the multi-byte write mode can start from any internal address. the master sends the data bytes, and each one is acknowledged. the master terminates the transfer by generating a stop condition. the sub-address decides the starting byte. for example, a multi-byte with sub-address 01h and 2 data_in bytes changes the b_counter and a_counter registers (01h,02h), and a multi-byte with sub-address 00h and 6 data_in bytes changes all the STW81103 registers. 6.1.7 current byte address read mode in the current byte address read mode, following a start condition, the master sends the device address with the rw bit set to 1. note that no sub-address is needed since there is only one read register. the STW81103 acknowledges this and outputs the data byte. the master does not acknowledge the received byte, and terminates the transfer with a stop condition. table 11. single-byte write mode s 1100a 2 a 1 a 0 0 ack sub-address byte ack data in ack p table 12. multi-byte write mode s 1100a 2 a 1 a 0 0 ack sub-address byte ack data in ack ??. data in ack p table 13. current byte address read mode s 1100a 2 a 1 a 0 1 ack data out no ack p
i 2 c bus interface STW81103 30/53 6.2 timing specification figure 23. data and clock figure 24. start and stop table 14. data and clock timing specifications symbol parameter minimum time units t cs data to clock setup time 2 ns t ch data to clock hold time 2 ns t cwh clock pulse width high 10 ns t cwl clock pulse width low 5 ns t c s t ch t cwh t cwl s da s cl tt s t a rt s top s da s cl
STW81103 i 2 c bus interface 31/53 figure 25. ack table 15. start and stop timing specifications symbol parameter minimum time units t start clock to data start time 2 ns t stop data to clock down stop time 2 ns table 16. ack timing specifications symbol parameter minimum time units t d1 ack begin delay 2 ns t d2 ack end delay 2 ns s cl s da t d1 t d2 89
i 2 c bus interface STW81103 32/53 6.3 i 2 c registers the STW81103 has 6 write-only registers and 1 read-only register. 6.3.1 write-only registers ta b l e 1 7 gives a short description of the write-only registers. functional_mode the bits pd[4:0] allow to select different functional modes for the STW81103 synthesizer according to the ta b l e 1 8 . table 17. write-only registers hex code dec code description 0x00 0 functional_mode 0x01 1 b_counter 0x02 2 a_counter 0x03 3 ref_divider 0x04 4 control 0x05 5 calibration msb lsb b7 b6 b5 b4 b3 b2 b1 b0 outbuf_ctrl_en cal_autostart_en pd4 pd3 pd2 pd1 pd0 b11 outbuf_ctrl_en: output buffer control mode enable (0 = off; 1 = on) cal_autostart_en: vco calibration auto-restart enable (0 = off; 1 = on) table 18. functional modes decimal value pd[6:0] description 0 power down mode 1 enable vco a, output frequency divided by 2 2 enable vco b, output frequency divided by 2 3 enable external vco, output frequency divided by 2 4 enable vco a, output frequency divided by 4 5 enable vco b, output frequency divided by 4 6 enable external vco, output frequency divided by 4 7 enable vco a, direct output 8 enable vco b, direct output 9 enable external vco, direct output
STW81103 i 2 c bus interface 33/53 b_counter b[10:3]. b counter value (bit b11 in the previous register, bits b[2:0] in the next register) a_counter bits b[2:0] for b_counter, a_counter values. ref_divider reference clock divider ratio r[9:1] (bits r1, r0 in the next register). control the control register is used to set the charge pump current, the vco output voltage amplitude and the prescaler modulus: the lo output frequency is programmed by setting the proper values for a, b and r according to the following formula: and p is the selected prescaler modulus. msb lsb b7 b6 b5 b4 b3 b2 b1 b0 b10b9b8b7b6b5b4b3 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 b2 b1 b0 a4 a3 a2 a1 a0 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 r9 r8 r7 r6 r5 r4 r3 r2 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 r1 r0 pll_a1 pll_a0 cpsel2 cpsel1 cpsel0 psc_sel pll_a[1:0]: vco amplitude cpsel[2:0]: charge pump output current psc_sel: prescaler modulus select ('0' for p=16, '1' for p=19) where d r equals { 1 for direct output 0.5 for output divided by 2 0.25 for output divided by 4 f out d r b ( pa ) f ref clk ? r ---------------------------------- - + =
i 2 c bus interface STW81103 34/53 calibration this register controls the vco calibrator using the following values: 6.3.2 read-only register this register is automatically addressed in the ?current byte address read mode?, using the following values: 6.3.3 default configuration at power on, all the bits are set to '0'. consequently the part starts in power down mode. msb lsb b7 b6 b5 b4 b3 b2 b1 b0 initcal sercal selextcal cal4 cal3 cal2 cal1 cal0 initcal: for test purposes only, must be set to 0 sercal: at 1 starts the vco auto-calibration (automatically reset to 0 at the end of calibration) selextcal: for test purposes only; must be set to 0 cal[4:0]: for test purposes only; must be set to 0 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 dev_id1 dev_id0 lock_det intcal4 intcal3 intcal2 intcal1 intcal0 dev_id[1:0]: device identifier bits; returns ?10? lock_det: 1 when pll is locked intcal[4:0]: internal value of the vco control word
STW81103 i 2 c bus interface 35/53 6.4 vco calibration procedure calibration of the vco center frequency is activated when the sercal bit (calibration register bit[6]) is set to 1. to program the device properly while ensuring vco calibration, perform the following steps before every channel change: 1. program all the registers using a multi-byte write sequence with the desired settings (functional mode, b and a counters, r counter, vco amplitude, charge pump, prescaler modulus), and all the bits of the calibration register (05h) set to 0. 2. program the calibration register using a single-byte write sequence (subaddress 05h) with the sercal bit set to 1. the maximum allowed pfd frequency (f pfd ) during calibration is 1 mhz; if you want a f pfd higher than 1 mhz, perform the following additional steps: perform all the steps of the calibration procedure, making sure to program the desired vco frequency with proper settings for the r, b and a counters so that f pfd is 1 mhz. program the device with the desired vco and pfd frequency settings according to step 1) above. 6.4.1 vco calibration auto-restart feature the vco calibration auto-restart feature can be enabled in two steps: 1. set the desired frequency ensuring vco calibration as described above (section 6.4) 2. program the functional_mode register (sub-address 00h) using a single-byte write sequence with the cal_autostart_en bit set to '1' while keeping unchanged the others.
spi digital interface STW81103 36/53 7 spi digital interface 7.1 general features the spi digital interface is selected by hardware connection of pin #21 (dbus_sel) to 3.3 v. the STW81103 ic is programmed by means of a high-speed serial-to-parallel interface with write option only. the 3-wire bus can be clocked at a frequency as high as 100 mhz to allow fast programming of the registers containing the data for rf ic configuration. the chip is programmed through serial words with a full length of 26 bits. the first 2 msbs represent the address of the registers, and the 24 lsbs represent the value of the registers. each data bit is stored in the internal shift register on the rising edge of the clock signal. the outputs of the selected register are sent to the device on the rising edge of the load signal. figure 26. spi input and output bit order l as t b it s ent (l s b)0 2 2 3 24 25(m s b) a1 load #4 addre ss decoder 1 data load reg.#4 reg.#1 reg.#0 d2 3 (m s b) d0 (l s b)
STW81103 spi digital interface 37/53 7.2 timing specification figure 27. spi timing specification table 19. spi data structure (msb is sent first) msb lsb address data for register (24 bits) a1 a0 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 20. address decoder and outputs address outputs a1 a0 databits d23-d0 no name function 0024 0st1 reference divider, vco amplitude, vco calibration, charge pump current, prescaler modulus 0 1 24 1 st2 functional modes, vco dividers 1024 2st3 reserved 1124 3st4 reserved d a t a m s bm s b-1 l s b t s et u p tdk clk_lo a dr tlo a d t t thold clock lo a d clk_lo a df table 21. spi timing specification symbol parameter min. typ. max. units t setup data to clock setup time 0.8 ns t hold data to clock hold time 0.2 ns t clk clock cycle period 10 ns t load load pulse width 3 ns t clk_loadr clock to load rising edge 2 ns t clk_loadf clock to load falling edge 0.5 ns
spi digital interface STW81103 38/53 7.3 bit tables table 22. bits at 00h and st1 serial interface address = 00h register name = st1 bit name description [23] r9 reference clock divider ratio [22] r8 [21] r7 [20] r6 [19] r5 [18] r4 [17] r3 [16] r2 [15] r1 [14] r0 [13] pll_a1 vco amplitude control [12] pll_a0 [11] cpsel2 charge pump output current control [10] cpsel1 [9] cpsel0 [8] psc_sel prescaler modulus select (0 for p=16, 1 for p=19) [7] initcal for test purposes only; must be set to 0 [6] sercal enable vco calibration (see section 7.4 ) [5] selextcal for test purposes only; must be set to ?0? [4] cal4 for test purposes only; must be set to ?0? [3] cal3 [2] cal2 [1] cal1 [0] cal0
STW81103 spi digital interface 39/53 table 23. bits at 01h and st2 serial interface address = 01h register name = st2 bit name description [23] outbuf_ctrl_en output buffer control mode enable (0 = off, 1 = on) [22] cal_autostart_en vco calibration auto restart enable (0 = off, 1 = on) [21] pd4 device functional modes: 0. power down 1. enable vco a, output frequency divided by 2 2. enable vco b, output frequency divided by 2 3. enable external vco, output frequency divided by 2 4. enable vco a, output frequency divided by 4 5. enable vco b, output frequency divided by 4 6. enable external vco, output frequency divided by 4 7. enable vco a, direct output 8. enable vco b, direct output 9. enable external vco, direct output [20] pd3 [19] pd2 [18] pd1 [17] pd0 [16] b11 b_counter bits [15] b10 [14] b9 [13] b8 [12] b7 [11] b6 [10] b5 [9] b4 [8] b3 [7] b2 [6] b1 [5] b0 [4] a4 a_counter bits [3] a3 [2] a2 [1] a1 [0] a0
spi digital interface STW81103 40/53 the lo output frequency is programmed by setting the proper value for a, b and r according to the following formula: and p is the selected prescaler modulus. 7.3.1 default configuration at power on, all the bits are set to '0'. consequently the part starts in power down mode. 7.4 vco calibration procedure calibration of the vco center frequency is activated when the sercal bit (st1 register bit[6]) is set to 1. to program the device properly while ensuring vco calibration, perform the following steps before every channel change: 1. program the st2 register with the desired settings (functional mode, b and a counters). 2. program the st1 register with the desired settings (r counter, vco amplitude, charge pump, prescaler modulus) and with the sercal bit set to 1. the maximum allowed pfd frequency (f pfd ) during calibration is 1 mhz; if you want a f pfd higher than 1 mhz, perform the following additional steps: perform all the steps (step 1 and 2 above) of the calibration procedure, making sure to program the desired vco frequency with proper settings of the r, b and a counters so that f pfd is 1 mhz. program the device with the desired vco and pfd frequency settings as per steps 1 and 2 above with sercal bit set to 0. 7.4.1 vco calibration auto-restart feature the vco calibration auto-restart feature can be enabled in two steps: 1. set the desired frequency ensuring vco calibration as described above ( section 7.4 ) 2. program the st2 register with the cal_autostart_en bit set to '1' while keeping unchanged the others. where d r equals { 1 for direct output 0.5 for output divided by 2 0.25 for output divided by 4 f out d r bpa + () f ref clk ? r ---------------------------------- - =
STW81103 application information 41/53 8 application information the STW81103 features three different alternately selectable bands: direct output (2.5 to 3.05 ghz and 4.35 to 5.0 ghz), divided by 2 (1.25 to 1.525 ghz and 2.175 to 2.5 ghz) and divided by 4 (625 to 762.5 mhz and 1087.5 to 1250 mhz). to achieve a suitable power level, a good matching network is necessary to adapt the output stage to a 50 load. moreover, since most commercial rf components have single-ended input and output terminations, a differential to single-ended conversion may be required. the different matching configurations shown below for each of the three bands are suggested as a guideline when designing your own application board. inside the evaluation kit is the ads design for each matching configuration suggested in this chapter. the name of the corresponding ads design is given in each figure. the ads designs provide only a first indication of the output stage matching, and should be reworked according to the choices of layout, board substrate, components and so on. the ads designs of the evaluation boards are provided with a complete electromagnetic modelling (board, components, and so on). 8.1 direct output if you do not need a differential to single conversion, you can match the output buffer of the STW81103 in the simple way shown in figure 28 . this illustrates the differential to single- ended output network in the 2.5 - 5.0 ghz range (match_lc_lump_4g_diff.dsn). figure 28. differential/single-ended output network (match_lc_lump_4g_diff.dsn) since most discrete components for microwave applications are single-ended, you can easily use one of the two outputs and terminate the other one to 50 with a 3 db power loss. rf 100 ohm 50 ohm 100 ohm 5.5nh 5.5nh 10pf 50 ohm 10pf vcc vcc outp rf outn
application information STW81103 42/53 alternatively, you can combine the two outputs in other ways. a first topology for the direct output (2.5 to 5.0 ghz) is suggested in figure 29 . it basically consists of a simple lc balun and a matching network to adapt the output to a 50 load. the two lc networks shift output signal phase of -90 and +90, thus combining the two outputs. this topology, designed for a center frequency of 4 ghz, is intrinsically narrow-band since the lc balun is tuned at a single frequency. if the application requires a different sub-band, the lc combiner can be easily tuned to the frequency of interest. figure 29. lc lumped balun and matching network (match_lc_lump_4g.dsn) the 1.9 nh shunt inductor works as a dc feed for one of the open collector terminals as well as a matching element along with the other components. the 1.9 nh series inductors are used to resonate the parasitic capacitance of the chip. for optimum output matching, it is recommended to use 0402 murata or avx capacitors and 0403 or 0604 hq coilcraft inductors. it is also advisable to use short interconnection paths to minimize losses and undesired impedance shift. an alternative topology that permits a more broadband matching as well as balanced to unbalanced conversion, is shown in figure 30 . rf 50 ohm 50 ohm 50 ohm 1. 9 nh 1. 9 nh 0. 8 pf 0. 8 pf 1. 9 nh 1. 9 nh 0. 8 pf 0. 8 pf 2.5pf vcc vcc outp rf outn
STW81103 application information 43/53 figure 30. evaluation board (evb4g) matching network (match_evb4g.dsn) for differential to single conversion, the 50 to 100 johanson balun is recommended (3700bl15b100). 8.2 divided by 2 output if your application does not require a balanced to unbalanced conversion, the output matching reduces to the simple circuit shown below ( figure 31 ), which illustrates a differential to single-ended output network in the 1.25 - 2.5 ghz range (match_lc_lump_2g_diff.dsn). you can easily use this solution to provide one single- ended output that terminates the other output at 50 with a 3 db power loss. figure 31. differential/single-ended output network (match_lc_lump_2g_diff.dsn) 1pf 1pf 1.2pf 1.2pf 4.7pf 12pf rf 50 ohm 50 ohm 50 ohm 5.5nh 5.5nh 12pf 2:1 12pf vcc vcc outp rf outn rf 50 ohm 50 ohm 50 ohm 22nh 22nh 10pf 50 ohm 10pf vcc vcc outp rf outn
application information STW81103 44/53 a first solution to combine the differential outputs is the lumped lc type balun tuned in the 2 ghz band ( figure 32 ). figure 32. lc lumped balun for divided by 2 output (match_lc_lump_2g.dsn) the same recommendation for the smd components also applies to the divided by 2 output. another topology suited to combining the two outputs for the divided by 2 frequencies is represented in figure 33 . figure 33. evaluation board (evb2g) matching network (match_evb2g.dsn) rf 50 ohm 50 ohm 50 ohm 2.7nh 2.7nh 2pf 2pf 2.7nh 2.7nh 3 nh 2pf 2pf 3 pf vcc vcc outp rf outn 1.2pf 22pf rf 50 ohm 50 ohm 50 ohm 5.5nh 1. 9 nh 5.5nh 22pf 2:1 22pf vcc vcc outp rf outn
STW81103 application information 45/53 for differential to single conversion, the 50 to 100 johanson balun (1600bl15b100) is recommended. 8.3 divided by 4 output the topology, components, values and considerations of figure 31 also apply to the divided by 4 output (match_lc_lump_1g_diff.dsn). as for the previous sections, a solution to combine the differential outputs is the lumped lc type balun tuned in the 1 ghz band ( figure 34 ). figure 34. lc lumped balun for divided by 4 output (match_lc_lump_1g.dsn) if you prefer to use an rf balun, you can adapt the topology depicted in figure 33 , and change the balun and the matching components ( figure 35 ). the suggested balun for the 0.625 - 1.25 ghz frequency range is the 1:1 johanson 900bl15c050. rf 25 ohm 50 ohm 25 ohm 5.5nh 5.5nh 4pf 4pf 5.5nh 5.5nh 14nh 4pf 4pf 6pf vcc vcc outp rf outn
application information STW81103 46/53 figure 35. evaluation board (evb1g) matching network (match_evb1g.dsn) 8.4 evaluation kit an evaluation kit can be delivered upon request, including the following: evaluation board gui (graphical user interface) to program the device measured s parameters of the rf output ads2005 schematics providing guidelines for application board design stwpllsim software for pll loop filter design and noise simulation application programming interface (api) three different evaluation kits are available, each optimized for one of the following frequency ranges: 1ghz 2ghz 4ghz when ordering, please specify one of the following order codes: the three evaluation kits differ only for the output stage network and can be adapted from one frequency band variant to a different one replacing properly the matching components and the balun. 0.5pf 22pf rf 25 ohm 50 ohm 25 ohm 1 8 nh 2.1nh 1 8 nh 8 .2pf 1:1 8 .2pf vcc vcc outp rf outn table 24. order code of the evaluation kit part number description STW81103-evb1g 1 ghz frequency range - divider by 4 output optimized STW81103-evb2g 2 ghz frequency range - divider by 2 output optimized STW81103-evb4g 4 ghz frequency range - direct output optimized
STW81103 application diagram 47/53 9 application diagram figure 36. typical application diagram note: 1 see section 8: application information for further information on output matching topology. 2 ext_pd, add2, add1 (and add0 when the i 2 c bus is selected) can be hard wired directly on the board. 3 loop filter values are for f step = 200 khz. 4 for best performance vdd 1 must be a low noise supply (20 v rms in 10 hz-100 khz bw). vdd_ e s d vdd_vcoa dbu s _ s el sc l/cl k sda/ data e xt_p d add 1 add0/ loa d add 2 v dd_d bus vdd_div2 vdd_outbuf outbufp outbufn vdd_div4 vdd_vcob vc t rl ic p re x t vd d _cp t e s t1 lo c k_det vdd_bufvco extvco_inp extvco_inn vdd_pll ref_clk te s t2 10 p 22 p 1 n 10 p 22p 1n 270p 6 8 p 2.7n 10 22p 1n 51 1. 8 n STW81103 from/to microcontroller to microcontroller loop filter vdd 1 rf o u t ref clk vdd 1 vdd 1 vdd 1 vdd 1 vdd 2 10 p 22p 1n i2c s pi 100 100 15p 15p 100 15p 4.7k 8 .2k 2.2k
application diagram STW81103 48/53 figure 37. ping-pong architecture diagram note: 1 see section 8: application information for further information on output matching topology. 2 ext_pd, add2, add1 (and add0 when the i 2 c bus is selected) can be hard wired directly on the board. 3 loop filter values are for f step = 200 khz. 4 for best performance vdd 1_1 and vdd 1_2 must be low noise supplies (20 v rms in 10 hz-100 khz bw). 9 ''b(6' 9''b9&2$ '%86 b6(/ 6&/&/. 6'$'$7$ (;7b3' $'' $''/2$' $'' 9''b'%86 9''b',9 9''b287%8) 287%8)3 287%8)1 9''b',9 9''b9&2% 9&75/ ,&3 5(;7 9''b&3 7(67 / 2&.b'(7 9''b %8)9&2 (;79&2 b ,13 (;79&2 b,11 9''b 3// 5()b&/. 7(67 n s s n q q s m q 67: 'hylfh/rfnhgdw)uht ) 2xwsxw%xiihu&rqwuro0rghhqdeohg wrplfurfrqwuroohu orrsilowhu 5)2xw uhifon 9'' b 9'' b 9'' b 9'' b ,& 63, q s m q s m qs m q s m n s s n q q s m q 67: 'hylfh /rfnhgdw)uht ) 2xwsxw%xiihu&rqwuro0rghhqdeohg wrplfurfrqwuroohu orrsilowhu 9'' b 9'' b 9'' b 9'' b ,& 63, qs m q s m qs m qs m 9'' 9'' 9'' 9'' 9'' 9'' 9 ''b (6' 9''b9&2$ '%86b6(/ 6&/&/. 6'$'$ 7$ (; 7b 3' $'' $''/2$' $ '' 9''b'%86 9''b',9 9''b287%8) 287%8)3 287%8)1 9''b',9 9''b9&2% 9&75/ ,&3 5(;7 9''b&3 7(6 7 / 2&.b'( 7 9''b %8)9&2 (;79&2 b ,13 (;79&2 b,11 9''b 3// 5()b &/. 7(67 2xwsxw%xiihu +:&rqwuro plfurfrqwuroohu
STW81103 application diagram 49/53 figure 38. application diagram with external vco (lo output from STW81103) note: see section 8: application information for further information on output matching topology. figure 39. application diagram with external vco (lo output from vco) 9''b(6' 9''b 9&2$ '%86b6(/ 6&/ &/. 6'$'$7$ (;7b3' $'' $''/ 2$' $'' 9''b'%86 9''b',9 9''b287%8) 287%8)3 287%8)1 9''b ',9 9''b9&2% 9&75/ ,&3 5(;7 9''b&3 7(67 /2 &. b'(7 9''b%8)9&2 (;79&2 b,13 (;79&2 b,11 9''b3// 5()b&/. 7(67 n & & 5 & 5 qs m q 67: orrsilowhu 9'' 9'' ,& 63, q s m q s m qs m )urpwr plfurfrqwuroohu 9'' 9'' /22xw 9'' 9'' 9&75/ 287 uhifon 9'' wr plfurfrqwuroohu 9''b(6' 9''b9&2$ '%86b 6(/ 6&/ &/. 6'$'$7$ (;7b3' $'' $''/2$' $'' 9''b'%86 9''b ',9 9''b 287%8) 287%8)3 287%8)1 9''b',9 9''b9&2% 9&75/ ,&3 5(;7 9''b&3 7(67 /2 &. b'(7 9''b %8)9&2 (;79&2 b ,13 (;79&2 b ,11 9''b 3// 5()b&/. 7(67 n & & 5 & 5 qs m q 67: orrsilowhu 9'' 9'' ,& 63, q s m uhifon 9'' 9&75/ 287 /22xw )urpwr plfurfrqwuroohu wr plfurfrqwuroohu
package mechanical data STW81103 50/53 10 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages, which have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: http://www.st.com. figure 40. vfqfpn28 mechanical drawing note: 1 vfqfpn stands for thermally enhanced very thin fine pitch quad flat package no lead. (very thin: a=1.00 max) 2 details of the terminal 1 identifier are optional, but if given, must be located on the top surface of the package by using either a mold or marked features.
STW81103 package mechanical data 51/53 table 25. package dimensions ref. min. typ. max. unit a 0.800 0.900 1.000 mm a1 0.020 0.050 mm a2 0.650 1.000 mm a3 0.200 mm b 0.180 0.250 0.300 mm d 4.850 5.000 5.150 mm d1 4.750 mm d2 2.950 3.100 3.250 mm e 4.850 5.000 5.150 mm e1 4.750 mm e2 2.950 3.100 3.250 mm e 0.500 mm l 0.350 0.550 0.750 mm p 0.600 mm k 14 degrees ddd 0.080 mm
ordering information STW81103 52/53 11 ordering information 12 revision history table 26. order codes part number temp range, c package packing STW81103at -40 to 85 vfqfpn28 tray STW81103atr -40 to 85 vfqfpn28 tape and reel table 27. document revision history date revision changes 18-jul-2007 1 initial release. 14-aug-2007 2 added chapter 8: application information . modified section 6.4: vco calibration procedure , and pin #23 description in ta bl e 1 . 28-mar-2008 3 updated table 1: pin description . updated table 2: absolute maximum ratings , table 3: operating conditions , table 5: electrical specifications and table 6: phase noise specification . updated section 5.8.2: vco frequency calibration . added vco calibration auto-restart feature . updated section 5.8.3: vco voltage amplitude control . added section 5.9: output stage and section 5.10: external vco buffer . updated functional_mode and calibration registers. added section 6.3.3: default configuration . updated section 6.4: vco calibration procedure and added section 6.4.1: vco calibration auto-restart feature . updated table 23: bits at 01h and st2 . added section 7.3.1: default configuration . updated section 7.4: vco calibration procedure and added section 7.4.1: vco calibration auto-restart feature . added ?application program interface api? item in section 8.4 . modified notes after figure 36 . added figure 37 , figure 38 and figure 39 . modified figure 40 .
STW81103 53/53 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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